1. Field of the Invention
The present invention relates to a solid state imaging device employing a MOS image sensor of a threshold voltage modulation system, which is employed in a video camera, an electronic camera, an image input camera, a scanner, a facsimile, or the like, and a method of driving. the same.
2. Description of the Related Art
Since semiconductor image sensors such as a CCD image sensor, a MOS image sensor, etc. are excellent in mass productivity, they are applied to most image input devices with the development of pattern miniaturizing technology.
In particular, the MOS image sensor is looked at once again in recent years because such MOS image sensor has smaller power consumption than the CCD image sensor and also the sensor device and its peripheral circuit devices can be fabricated by the same CMOS technology.
In light of such tendency of society, inventors of the present invention improved the MOS image sensor, then filed a Patent Application (Patent Application Hei 10-186453) in connection with the sensor device that has a carrier pocket (high concentration buried layer) under a channel region, and then obtained a Patent (registration number 2935492).
This MOS image sensor has a circuit configuration shown in FIG. 1A of this application, and takes an initializing period, a storing period, and a reading period in operation, as shown in FIG. 1B. In the initializing period, the channel region is brought into the depletion state by applying a high reverse voltage to electrodes to discharge light generating holes that remain in a hole pocket. In the storing period, the light generating holes are generated by the light irradiation and stored into the hole pocket. In the reading period, a light signal that is in proportion to a storage amount of the light generating holes is detected.
In the invention according to the Patent (registration number 2935492), as shown in FIGS. 1A, 1B of this application, a signal impedance is reduced by a source follower using the combination of a light signal detecting MOS transistor 312 and an active load such as a constant current source 306, etc. provided on the outside, a source potential is detected, a memory capacity (not shown) is charged, and a voltage signal is output.
200 of the other reference symbols is a vertical output line, 201 a VSCAN supply line, 202 a VDD supply line, 206 a horizontal output line, 301 a unit pixel, 302 a VSCAN drive scanning circuit, 303 a VDD drive scanning circuit, 304 an input scanning circuit, 305 a switch, 307 an output terminal, and 311 a photo diode. The detail description for the circuit configuration and the operation may refer to the Patent (registration number 2935492).
However, when wiring widths are reduced since pixels are miniaturized, parasitic resistance values are increased. Thus, variation in voltage drop in the wirings and between the wirings due to series resistance becomes an issue.
Therefore, when a current value is reduced in order to suppress the voltage drop, a rate of occupying a sub-threshold current (characteristic immediately before the leading of the drain current in the drain voltage-drain current characteristic) to a source current due to the drain-induced barrier lowering (DIBL) is increased relatively if a channel length is short. Therefore, since an output voltage is put under the control of the sub-threshold current, variation in modulation of the output voltage is increased.
It is an object of the present invention to provide a solid state imaging device which is capable of suppressing the influence of variation in a sub-threshold current and reducing variation in modulation of an output voltage, and a method of driving the same.
According to the present invention, the light signal detecting insulated gate field effect transistor in the pixel is the threshold-modulated type light signal detecting insulated gate field effect transistor which is provided with the high concentration buried layer under a channel and which accumulates light generating charges under the channel is employed, therefore a channel length thereof is long.
For this reason, the electric fields from the drain regions are relaxed. Hence, the threshold variation is made small and in turn variation in the sub-threshold current is made small, therefore the charging current can be minimized. As a result, since potential reduction due to the parasitic resistance such as the wiring, etc. can be suppressed, the direct coupling with the capacitive load can be attained.
Also, a finite time is needed to load line memories. But the loading time into the line memories is considerably shorter than the noise voltage-reading period and the reading period. Therefore, the loading into the line memories can be finished in the noise voltage-reading period, or the like.
By the way, if a plurality of line memories are aligned in parallel, these parasitic capacitances are connected in parallel with the line memories to be read, and the first and second source potentials stored in the line memories to be read are output via the so-called switched capacitor circuit. At this time, since the charge transfer is caused in the switched capacitor circuit by the first operational amplifier, the parasitic capacitance viewed from the output side of the switched capacitor circuit can be reduced. Thus, a reading speed is seldom affected even if a plurality of line memories are aligned in parallel. Also, such advantage can be achieved that, since the influence of the parasitic capacitance is small, the maximum gain can be obtained.
In addition, the preset voltage which is higher than a ground potential but lower than the stored source potential can be stored in the first line memory and the second line memory prior to storage of the source potential by connecting a means for applying a preset voltage to the first line memory and the second line memory. Accordingly, an operation of the light signal detecting insulated gate field effect transistor can be cut off without fail while the ground potential is being applied to the gate electrode of the light signal detecting insulated gate field effect transistor, whereby a leakage current can be minimized.
The transmission gates formed of the CMOS transistors are used as the first switch circuit and second switch circuit, and thus a higher signal voltage can be passed through the transmission gate. In this case, when a higher voltage is applied to the source region of the light signal detecting insulated gate field effect transistor, the transmission gates come not to work normally by the reason why the pn junction of the source/drain region in the p channel MOS transistor of CMOS transistors constituting the transmission gate is biased to a forward direction.
In order to avoid this, a high voltage blocking switch circuit is provided on the vertical output line between the first switch circuit and the second switch circuit and the source region of the light signal detecting insulated gate field effect transistor. Or a first high voltage blocking switch circuit is provided between the first switch circuit and the source region, and a second high voltage blocking switch circuit is provided between the second switch circuit and the source region. Accordingly, the above trouble can be prevented by cutting a connection between the first switch circuit and the source region and a connection between the second switch circuit and the source region during an initializing period when a high voltage is applied to the source region in order to sweep out the charges stored in the high concentration buried layer.